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207

XMEGA A [MANUAL]

8077I–AVR–11/2012

Figure 19-6. Master read transaction.

Assuming the slave acknowledges the address, the master can start receiving data from the slave. There are no

limitations to the number of data packets that can be transferred. The slave transmits the data while the master signals

ACK or NACK after each data byte. The master terminates the transfer with a NACK before issuing a STOP condition.

Figure 19-7 illustrates a combined transaction. A combined transaction consists of several read and write transactions

separated by repeated START conditions (Sr).

Figure 19-7. Combined Transaction.

19.3.7 Clock and Clock Stretching

All devices connected to the bus are allowed to stretch the low period of the clock to slow down the overall clock

frequency or to insert wait states while processing data. A device that needs to stretch the clock can do this by

holding/forcing the SCL line low after it detects a low level on the line.

Three types of clock stretching can be defined, as shown in Figure 19-8.

Figure 19-8. Clock stretching(1).

Note:

Clock stretching is not supported by all I2C slaves and masters.

If a slave device is in sleep mode and a START condition is detected, the clock stretching normally works during the

wake-up period. For AVR XMEGA devices, the clock stretching will be either directly before or after the ACK/NACK bit,

as AVR XMEGA devices do not need to wake up for transactions that are not addressed to it.

A slave device can slow down the bus frequency by stretching the clock periodically on a bit level. This allows the slave

to run at a lower system clock frequency. However, the overall performance of the bus will be reduced accordingly. Both

the master and slave device can randomly stretch the clock on a byte level basis before and after the ACK/NACK bit.

This provides time to process incoming or prepare outgoing data, or perform other time-critical tasks.

In the case where the slave is stretching the clock, the master will be forced into a wait state until the slave is ready, and

vice versa.

ADDRESS

DATA

Transaction

Address Packet

Data Packet

N data packets

A/A

R/W

DATA

A/A

ADDRESS

DATA

R/W

ADDRESS

Transaction

Address Packet #1

N Data Packets

M Data Packets

Address Packet #2

Direction

SDA

SCL

ACK/NACK

bit 0

bit 7

bit 6

Periodic clock

stretching

Random clock

stretching

Wakeup clock

stretching

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